Semiconductor Engineering

Why Every Design IP Needs A Complete QA Methodology

Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables ...
Business Wire

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification ...
Semiconductor Engineering

Using IP-XACT To Solve Design And Verification Problems

As today’s SoC designs grow more complex and time-to-market (TTM) pressures rise, designers are looking for techniques to build and update designs easily. Key elements for addressing these SoC ...
EDN

Pcell and IP realities for fabless design

The current methodology for SOC (system-on-chip) design employs a hierarchical approach that maximizes the use of IP (intellectual-property) blocks. This method replaces the previous one, which used ...
EDN

FPGA PHY IP Design

This application note describes implementing and simulating the protocol-specific PHY intellectual property (IP) core in Stratix® V devices using the Interlaken PHY IP interface. You can use the ...
Electronic Design

IP Modeling Holds Key To Easier Design Reuse

Design and validation of IP at higher abstraction levels is finding support among synthesis-tool vendors as well. Pradeep Fernandes, director of technical marketing at Get2Chip, takes the position ...