Design-Reuse

Magma Unveils Talus ATPG and Talus ATPG-X – Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression

Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs ...
Semiconductor Engineering

Better ATPG To Minimize Chip Test Time And Cost

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...
Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...
Design-Reuse

On-time Finish Rests With Multiple Clocks

Today's leading-edge system-on-chip (SoC) designs typically have multiple clock domains and, in many cases, multiple internally generated clocks. In test mode, those clocks may be combined into one, ...