EDN

TSMC rolls 40-nm design flow

SAN JOSE, Calif. &#151 Paving the way for next-generation chips, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) today will roll out its latest design methodology for IC production at the ...
EDN

TSMC outlines reference tool flow for 65-nm design

TSMC will announce this week a new reference IC design flow for its recently unveiled 65-nm process, with an emphasis on low-power design. Concurrently, the company will announce new DFM (design for ...
Semiconductor Engineering

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The ...
Design-Reuse

Methodology for flow integrations in a SOC design

SOC design typically requires integration of multiple tool flows and methodologies that aid in realization of design goal. Integration of flows require standard interface with reference to Makeflow ...
Design-Reuse

Simplifying DSP Hardware Development within a MATLAB-based Design Flow

Historically, exploiting FPGA or ASIC implementation of DSP algorithms has been the domain of companies with highly-skilled designers and large budgets. Now, a new generation of tools is bringing ...
Semiconductor Engineering

C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems ...