Design-Reuse

Architectures: On-chip interconnect gets off the bus

Monterey, Calif. — Moderate-scale systems-on-chip (SoCs) have grown so similar that most can be described with a single block diagram. A central processor emits a processor-specific high-speed bus ...
EDN

Matrix Holds Key To On-chip Interconnect

The advent of 0.13-micron and even 0.1-micron semiconductor manufacturing processes has given the system-on-a-chip designer many more gates with which to work. But in a lot of cases, both the system ...
Semiconductor Engineering

A Brief History Of The Interconnect

The high functional integration of system-on-chip designs today is driving the need for new technological approaches in semiconductor design. Anyone who owns a Samsung Galaxy S4, HTC One or comparable ...
EDN

PalmChip Bus Patent Threatens Most SoCs

A patent granted to PalmChip Corp. covers the techniques used to implement on-chip CPU bus structures in nearly all modern system-on-chip (SoC) designs, the company said. CPU or system-interconnect ...
Electronic Design

Interconnect IP Steers SoC Integration Into The Fast Lane

A nonblocking interconnect architecture smoothes the bumpy ride taken by SoC integration and IP reuse while ushering in a new abstraction level. Intellectual property (ip), and its reuse, is expected ...