EDN

The next RISC-V processor frontier: AI

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The Next Platform

Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter

Once a hyperscaler or a cloud builder gets big enough, it can afford to design custom compute engines that more precisely match its needs. It is not clear that the companies that make custom CPUs and ...
University of Vermont

RISC vs CISC

RISC (reduced instruction set computer), and CISC (complex instruction set computer). These two principles govern fundamental choices of CPU design and implementation. RISC architectures, such as ARM, ...
Forbes

SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI Workloads

Forbes contributors publish independent expert analyses and insights. Marco Chiappetta is a technologist who covers semiconductors and AI. SiFive just announced an array of new additions to its ...
Forbes

RISC-V’s Ascent Could Reshape The Global Compute Landscape

Forbes contributors publish independent expert analyses and insights. Dave Altavilla is a Tech Analyst covering chips, compute and AI. For decades, chip architectures have been dominated by a pair of ...
HotHardware

NVIDIA Confirms CUDA Support Is Coming To RISC-V And It's A Huge Deal

Old-timers might recall the idea of "RISC" as a once-upon-a-time processor design ideology. RISC processors were mostly used for servers from Sun Microsystems, DEC, and other companies of a bygone era ...
Digi Times

Tenstorrent pushes RISC-V into AI's fast lane with open chiplet strategy

The rise of AI and high-performance computing (HPC) is accelerating the adoption of RISC-V, the open-source instruction set architecture that is reshaping the global semiconductor landscape. At the ...
CoinDesk

Risc Zero’s 'Boundless' Incentivized Testnet Goes Live

Boundless, the decentralized zero-knowledge (ZK) compute marketplace powered by RISC Zero, has launched its incentivized testnet (which it is calling “Mainnet Beta”) on Base, Coinbase’s Ethereum layer ...
CoinTelegraph

What is RISC-V, and why does Vitalik Buterin want it for Ethereum smart contracts?

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...
csis.org

Sustaining Standards Leadership: The United States Cannot Disengage from RISC-V

RISC-V architecture is an open, international standard governing how software interfaces with hardware in a computer. It serves as a shared language that sets the parameters for communication and ...
Geeky Gadgets

How RISC-V is Disrupting x86 and ARM in 2025

Have you ever wondered if there’s a way to break free from the dominance of proprietary computing architectures like x86 and ARM? For decades, these platforms have dictated the rules of the game, ...
CoinDesk

Vitalik Buterin Proposes Replacing Ethereum’s EVM With RISC-V

Ethereum co-founder Vitalik Buterin shared a new proposal over the weekend that would radically overhaul the system that powers its smart contracts. Buterin's suggestion, which he posted on Ethereum's ...